Designers of modern complex integrated circuits (IC), which are increasingly implemented using deep-submicron and nanometer technologies, find that efficient test and debug techniques are indispensable for analyzing and improving the performance of the integrated circuits. Unfortunately, the increasingly smaller geometries of elements in integrated circuits, which place more and more elements in smaller areas and increase the overall number of circuit elements, make silicon testing and debugging more difficult. In fact, activities related to debugging very large scale integration (VLSI) circuits and chips are rapidly becoming major bottlenecks in overall IC production timelines.
Modern VLSI chips have stringent timing requirements due to the deep-submicron and nanometer technologies as well as the increasing complexities of the circuits. Consequently, delay faults and other types of timing errors have emerged as significant problems. Such timing errors may cause an otherwise functional chip to fail as its clock speed increases. Designers use debugging to ensure that the integrated circuits not only function, but that the circuits perform within desired specifications. While designers may use simulation to help ensure that a circuit meets its performance specifications, designers must nonetheless use debugging techniques on the circuit once it has actually been formed or implemented in silicon. Designers must use these silicon debugging techniques to detect faults which stem from numerous causes, such as logic errors, crosstalk, power supply fluctuations, timing errors, and delays due to physical implementation.
Designers use silicon debug probing tools to look at elements on a die, or even multiple elements at the same time. Such tools may allow the designers to locate timing errors and other types of faults by monitoring the operation of the elements of the circuit. The tools allow the designers to compare actual measured or otherwise observed states of the elements with their expected or simulated states. In other words, the designers locate mismatches of circuit elements by comparing the simulated passing cases with the measured or observed failing cases. Unfortunately, when trying to diagnose or analyze actual faults designers presently observe numerous elements that are not necessarily related to an actual failure. For example, the designers may spend time analyzing elements that exhibit mismatches, but those mismatches may be products of the fault and not possible causes. Stated differently, the designers may observe elements that indicate a mismatch, but those elements are not in the input paths to the actual failing node. Consequently, designers may consume considerable time trying to rule out which mismatches are actually related to the failure.